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In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that must pass before the design can be taped out. This implies an iterative process involving incremental fixes across the board in one or more check type and retesting the design. There are two types of sign-off's are there,namely Front-end sign-off and Back-end sign-off. After back-end sign-off the chip will go to Fabrication. After listing out all the features of specification, Verification Engineer will write coverage for those features and finds out bugs and sends back the RTL design to the designer.Bugs means missing of features,errors in design(typo and functional errors)etc.,.When the coverage reaches a maximum% then Verification team will sign it off. Basically by using a methodology like UVM,OVM or VMM, the verification team will develop a reusable environment. Nowadays UVM is getting more popular than others. == Check types == Signoff checks have become more complex as VLSI designs approach 22nm and below process nodes because of the increased impact of previously ignored (or more crudely approximated) second order effects. There are several categories of signoff checks. * DRC - Also sometimes known as geometric verification, this involves verifying if the design can be reliably manufactured given current photolithography limitations. In advanced process nodes, DFM rules are upgraded from optional (for better yield) to required. * LVS - Also known as schematic verification, this is used to verify that the placement and routing of the standard cells in the design has not altered the functionality of the constructed circuit. * Formal verification - Here, the logical functionality of the post-layout netlist (including any layout-driven optimization) is verified against the pre-layout, post-synthesis netlist. * Voltage drop analysis - Also known as IR-drop analysis, this check verifies if the power grid is strong enough to ensure that the voltage representing the binary high value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors. * Signal integrity analysis - Here, noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the threshold voltage of gates along the data path. * Static timing analysis (STA) - Slowly being superseded by statistical static timing analysis (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended clock frequency, especially under the effects of on-chip variation. STA is run as a replacement for SPICE, because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs. * Electromigration lifetime checks - To ensure a minimum lifetime of operation at the intended clock frequency without the circuit succumbing to electromigration. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Signoff (electronic design automation)」の詳細全文を読む スポンサード リンク
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